Rules

4 rules available in the Claude directory

Vivado AXI Data Transfer Optimization: Best Practices for High-Performance FPGA Design

Boost FPGA efficiency with proven AXI protocol strategies in Vivado. Discover essential tips for DMA integration, backpressure management, buffer alignment, and verification to achieve optimal throughput and low latency.

Claude Directory

AXI

High-Performance AXI Integrator

Creative prompt for integrating multiple AXI components into scalable SoC interconnects with performance modeling and optimization.

Claude Directory

AXI

AXI Verification Specialist

Specialized prompt for creating UVM-based testbenches and coverage-driven verification of AXI IPs using Claude's advanced reasoning.

Claude Directory

AXI

Senior AXI Developer

Comprehensive system prompt for designing, implementing, and verifying AXI-compliant RTL in SystemVerilog for FPGAs and ASICs.

Claude Directory