Rules
4 rules available in the Claude directory
Testing
Vivado AXI Data Transfer Optimization: Best Practices for High-Performance FPGA Design
Boost FPGA efficiency with proven AXI protocol strategies in Vivado. Discover essential tips for DMA integration, backpressure management, buffer alignment, and verification to achieve optimal throughput and low latency.
C
Claude DirectoryAXI
High-Performance AXI Integrator
Creative prompt for integrating multiple AXI components into scalable SoC interconnects with performance modeling and optimization.
C
Claude DirectoryAXI
AXI Verification Specialist
Specialized prompt for creating UVM-based testbenches and coverage-driven verification of AXI IPs using Claude's advanced reasoning.
C
Claude DirectoryAXI
Senior AXI Developer
Comprehensive system prompt for designing, implementing, and verifying AXI-compliant RTL in SystemVerilog for FPGAs and ASICs.
C
Claude Directory