doonny/PipeCNN

Free

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

FreeFree tier

Inputs: image

Type

Open Source

Visit Website GitHub (38 stars)

About doonny/PipeCNN

PipeCNN is an open-source, OpenCL-based FPGA accelerator designed for large-scale convolutional neural networks (CNNs). It leverages high-level synthesis (HLS) tools to enable faster hardware development cycles compared to traditional RTL design. The project provides a generic and efficient pipelined architecture that improves inference throughput and is scalable in both performance and hardware resources. PipeCNN supports both Intel OpenCL SDK and Xilinx Vitis design flows, and has been tested on several FPGA boards including Terasic DE5a-net, Intel Arria-10 Dev Kit, Xilinx U50, ZCU102, and ZC706. It comes with a ModelZoo containing pre-quantized models for VGG-16 and ResNet-50, and can run classification on the ImageNet dataset.

Key Features

OpenCL-based FPGA accelerator for large-scale CNNs

Pipelined CNN functional kernels for improved inference throughput

Scalable in performance and hardware resources

Supports both Intel OpenCL SDK and Xilinx Vitis design flows

Tested on multiple FPGA boards including Terasic DE5a-net, Intel Arria-10, Xilinx U50, ZCU102, ZC706

Includes pre-quantized models for VGG-16 and ResNet-50 via ModelZoo

Capable of ImageNet classification with top-1/5 accuracy measurement

Pros & Cons

Pros

Open-source and free to use
Generic design that can be deployed on various FPGA boards from Intel and Xilinx
Pipelined architecture improves inference throughput
Scalable to different resource budgets
Comes with pre-quantized models for popular networks (VGG-16, ResNet-50)
Supports both major FPGA vendor toolchains (Intel and Xilinx)

Cons

Performance may be outdated as the project was released several years ago
Limited to specific FPGA boards that have been tested (others may require additional effort)
Requires knowledge of OpenCL and FPGA development tools (Intel OpenCL SDK or Xilinx Vitis)
Only supports two pre-trained models out-of-the-box (VGG-16 and ResNet-50)
Documentation is primarily on GitHub; no dedicated support outside community

Best For

Accelerating CNN inference on FPGA hardwareDeploying pre-trained convolutional neural networks on diverse FPGA platformsRunning ImageNet classification tasks with FPGA accelerationResearch and development of HLS-based CNN accelerators

FAQ

What is PipeCNN?

PipeCNN is an open-source FPGA accelerator for convolutional neural networks, implemented using OpenCL and High Level Synthesis (HLS). It provides a pipelined design to improve inference throughput.

Which FPGA boards are supported?

Tested boards include Terasic DE5a-net (Arria-10), Intel Arria-10 Dev Kit, Xilinx U50, Xilinx ZCU102, and Xilinx ZC706. Other boards like DE10-standard, PAC cards, and Ultra96-v2 may work but are not verified.

What CNN models are available?

PipeCNN's ModelZoo provides pre-quantized models for VGG-16 and ResNet-50.

How do I run PipeCNN?

First download the pre-trained models and test data from the ModelZoo. Then compile the project using the provided Makefile, and run './run.exe conv.aocx'.

Does PipeCNN support ImageNet classification?

Yes, PipeCNN can run classification on the ImageNet validation dataset and measure top-1/5 accuracy by setting USE_OPENCV=1 in the Makefile and providing the dataset.