prompt

Free

AI-powered Verilog RTL architect for design, analysis, and repair

FreeFree tier

Type

Open Source

Visit Website GitHub (40 stars)

About prompt

Erie Verilog Generator is a specialized AI prompt from the ai-boost/awesome-prompts repository, designed to guide large language models (such as Codex) in generating, analyzing, and refining Verilog-2001 RTL designs. It supports multiple workflow modes—regular, deep_review, and agentic_repair—for new RTL generation and existing code analysis. The prompt enables a range of operations including static linting via a bundled Python script, self-checking testbench scaffold generation, semantic comparison, verification planning, and ASIC-quality review. All generated artifacts are structured as Verilog files, JSON reports, or Markdown documentation, making it suitable for both Chinese-language and English hardware design tasks.

Key Features

Verilog-2001 RTL generation guided by AI prompts

Three workflow modes: regular, deep_review, and agentic_repair

Existing RTL analysis with structured JSON and Markdown outputs

Semantic comparison between Verilog designs (equivalence, QoR, transform validation)

Static linting via bundled Python script (scripts/verilog_lint.py)

Self-checking testbench scaffold generation (scripts/tb_generator.py)

Verify-repair flow producing verification plan, log diagnosis, patch candidate, and simulation slice

Supports Chinese-language prompts and design descriptions

Automated workflow trace diagnosis and artifact extraction

Pros & Cons

Pros

Comprehensive skill covering generation, analysis, verification, and repair
Free and open-source (hosted on GitHub)
Produces structured artifacts (JSON, Markdown, Verilog) for easy integration
Supports both new RTL creation and existing code refinement
Includes optional independent lint and testbench generation scripts
Can be used with Chinese or English prompts

Cons

Requires an AI model (e.g., Codex) capable of following complex prompt instructions
Not a standalone tool; dependent on the underlying AI platform's capabilities
Limited to Verilog-2001 standard; does not cover newer SystemVerilog features
Setup may require familiarity with Python and command-line execution for helper scripts
The quality of output varies based on the AI model's training and context length

Best For

Chinese-language Verilog RTL design and generationAnalyzing and refining existing Verilog code for quality improvementDebugging and troubleshooting hardware designsASIC-quality review of Verilog RTL before tape-outCreating testbench scaffolds for simulation-based verificationComparing semantic equivalence of two Verilog designsLearning and teaching hardware description languages with AI assistance

FAQ

What is Erie Verilog Generator?

Erie Verilog Generator is an AI prompt (skill) from the awesome-prompts repository that enables large language models like Codex to generate, analyze, and verify Verilog-2001 RTL code. It provides structured workflows for design, repair, and validation.

What workflow modes are available?

Three modes: 'regular' (standard staged generation), 'deep_review' (adds an extra review stage), and 'agentic_repair' (evidence-driven repair flow for existing RTL).

Does it support existing Verilog code analysis?

Yes. It offers functions like analyze_existing_verilog, refine_existing_verilog, compare_verilog_semantics, and verify_existing_verilog, each producing specific structured outputs.

What are the helper scripts included?

Two Python scripts: verilog_lint.py for independent static linting and tb_generator.py for generating self-checking testbench scaffolds.