Vivado SystemVerilog Best Practices: Optimize FPGA Designs for Timing, Resources & Power

### Modular Design & Organization
**Do:** Split FPGA projects into compact, reusable components with precise interfaces for better maintainability and testing.
*Example:* Employ `interface` constructs to standardize signals between a top-level wrapper and sub-modules like a data processor and memory controller.

**Don't:** Build oversized, all-in-one blocks that hinder debugging and reuse.
*Example:* Avoid cramming ALU, registers, and I/O into a single file; instead, modularize early.

### Synchronous Logic Rules
**Do:** Stick to one clock domain when feasible and use synchronous resets for reliable flip-flop behavior.
*Example:* Declare `always_ff @(posedge clk) if (sync_rst) q <= 0; else q <= d;` to align resets with clock edges.

**Don't:** Mix asynchronous resets or multiple clocks without CDC handling, risking timing issues.
*Example:* Skip `always_ff @(posedge clk, posedge async_rst)` unless essential, as it complicates synthesis.

### Timing Management & Constraints
**Do:** Apply XDC constraints upfront and pipeline logic to fix STA violations on key paths.
*Example:* Add `[set_multicycle_path 2 -setup -from regA -to regB]` for paths needing extra cycles; insert registers like `stage1 <= combo_logic(input);`.

**Don't:** Ignore early STA reports or overload combo paths without optimization.
*Example:* Don't let a 20-LUT chain run unchecked; break it with flops for 300MHz targets.

### Resource & Synthesis Efficiency
**Do:** Infer BRAM/regs smartly and integrate Vivado IPs like AXI/DSP for optimal LUT/FF usage.
*Example:* Use `reg [7:0] mem [0:255];` to map dual-port RAM; configure AXI IP via Vivado GUI for burst transfers.

**Don't:** Over-register signals or skip IP reuse, wasting fabric resources.
*Example:* Avoid `reg [31:0] temp1, temp2;` for simple wires; let synthesis merge them.

### Power Reduction Strategies
**Do:** Gate clocks conditionally and enable power directives in synthesis.
*Example:* Implement `assign clk_en = enable && !idle; BUFGCE u_bufg (.CE(clk_en), .I(clk), .O(gated_clk));`.

**Don't:** Run idle clocks full-time without gating.
*Example:* Never connect raw `clk` to unused modules; gate it first.

### Verification & Debug
**Do:** Craft self-verifying testbenches with assertions and use ILA for hardware probes.
*Example:* `assert property (@(posedge clk) disable iff (rst) req |-> ##1 ack);` in modules/testbenches.

**Don't:** Rely on manual waveform checks alone; skip post-synth sims.
*Example:* Always run `xsim -gui top_behav` then `post-synth`, inserting ILA via `ila_0 probe0 (sig1, sig2);`.

### CDC & Performance Boosts
**Do:** Synchronize cross-domain signals with 2FF synchronizers or async FIFOs; tune AXI for throughput.
*Example:* `reg [1:0] sync_reg; always_ff @(posedge clk_b) sync_reg <= {sync_reg[0], sig_from_a};`.

**Don't:** Pass raw signals across domains or mishandle AXI backpressure.
*Example:* Use Gray-coded pointers in FIFOs, not binary, to prevent meta-stability.