Rules

2 rules available in the Claude directory

Vivado AXI Data Transfer Optimization: Best Practices for High-Performance FPGA Design

Boost FPGA efficiency with proven AXI protocol strategies in Vivado. Discover essential tips for DMA integration, backpressure management, buffer alignment, and verification to achieve optimal throughput and low latency.

Claude Directory

Testing

Vivado SystemVerilog Best Practices: Optimize FPGA Designs for Timing, Resources & Power

Master Vivado SystemVerilog best practices to build modular, high-performance FPGA designs. Learn Do/Don't tips for synchronous logic, timing closure, resource efficiency, power savings, and robust verification.

Claude Directory